Automatic mode selection circuit for semiconductor memory device

ABSTRACT

An automatic mode selection circuit for automatically selecting low voltage transistor transistor logic and high-speed input/output interface modes in a semiconductor memory device. The automatic mode selection circuit comprises an external reference voltage pad for delivering an external reference voltage, an internal reference voltage generator for generating an internal reference voltage, a power-on detector for detecting a power-on time point and then generating a pulse signal for a predetermined time period, a switching circuit for switching the external reference voltage from the external reference voltage pad and the internal reference voltage from the internal reference voltage generator in response to an output signal from the power-on detector, a reference voltage detector connected between the external reference voltage pad and the switching circuit for detecting the external reference voltage from the external reference voltage pad, a comparator for comparing an output voltage from the reference voltage detector with the internal reference voltage from the internal reference voltage generator in response to the output signal from the power-on detector, and a latch circuit for latching an output signal from the comparator and supplying the latched signal to an output terminal.

This application is a continuation application of U.S. patentapplication Ser. No. 08/580,200, filed Dec. 28, 1995, the entirecontents of which are hereby incorporated in their entirety nowabandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to automatic mode selectioncircuits for semiconductor memory devices, and more particularly to anautomatic mode selection circuit for a semiconductor memory device whichis capable of automatically selecting two modes of low voltagetransistor transistor logic (referred to hereinafter as LVTTL) andhigh-speed input/output (referred to hereinafter as I/O) interface inthe chip.

2. Description of the Prior Art

In a semiconductor memory device, there have recently been used a TTL orLVTTL and a high-speed I/O interface which are designed at bonding/metaloption, respectively. In order to overcome such two-mode design, therehas been proposed an automatic mode selection scheme for automaticallyselecting the two modes in the semiconductor chip.

FIG. 1 is a table illustrating the comparison between voltage levels ofthe LVTTL and high-speed I/O interface, FIG. 2 is a circuit diagramillustrating one example of the LVTTL, FIG. 3 is a circuit diagramillustrating one example of the high-speed I/O interface, and FIG. 4 isa waveform diagram illustrating output signals from the LVTTL andhigh-speed I/O interface in FIGS. 2 and 3.

As shown in FIG. 2, the LVTTL comprises a data output buffer 101, acomparator 102 and a parasitic capacitor C1. The parasitic capacitor C1is formed between the data output buffer 101 and the comparator 102. Thedata output buffer 101 includes a PMOS transistor Q1 connected between asupply voltage source Vdd and a node N1, and an NMOS transistor Q1connected between the node N1 and a ground voltage source Vss. Thecomparator 102 recognizes an output signal from the data output buffer101 as logic high when it reaches a voltage level of 2.4V. Thecomparator 102 also recognizes the output signal from the data outputbuffer 101 as logic low when it reaches a voltage level of 4.0V.

In FIG. 3, the high-speed I/O interface comprises a data output buffer103, a comparator 104, a termination voltage source Vtt and atermination resistor Rt. The data output buffer 103 has a limitedvoltage swing output characteristic by means of the termination resistorRt. The limited voltage swing output characteristic of the data outputbuffer 103 makes a high-speed operation possible.

The operations of the LVTTL and high-speed I/O interface with theabove-mentioned constructions will hereinafter be described withreference to FIG. 4 which is a waveform diagram illustrating outputsignals form the LVTTL and high-speed I/O interface in FIGS. 2 and 3.

In FIG. 4, the reference characters a and e designate high logic startpoints of the high-speed I/O interface and LVTTL, respectively. Thereference characters b and f designate high logic recognition points ofthe high-speed I/O interface and LVTTL, respectively. The referencecharacters c and g designate low logic start points of the high-speedI/O interface and LVTTL, respectively. The reference characters d and hdesignate low logic recognition points of the high-speed I/O interfaceand LVTTL, respectively. As seen from this drawing, the high-speed I/Ointerface can perform the operation at a much higher speed than that ofthe LVTTL, because of the limited voltage swing output characteristic.

FIG. 5 is a circuit diagram illustrating the construction of aconventional automatic mode selection circuit for a semiconductor memorydevice. As shown in this drawing, the conventional automatic modeselection circuit comprises a PMOS transistor Q5 connected between nodesN4 and N5, a PMOS transistor Q6 connected between the node N4 and a nodeN6, an NMOS transistor Q7 connected between the node N5 and a node N7,an NMOS transistor Q8 connected between the nodes N6 and N7, a PMOStransistor Q9 connected between a supply voltage source Vcc an a nodeN8, a reference voltage pad 202 for supplying a reference voltage Vrefto the node N8, and an inverter G1 connected between the node N6 and anode N9. The node N7 is connected to a ground voltage source Vss. ThePMOS transistors Q5 and Q6 have their gates connected in common to thenode N5. The NMOS transistor Q7 has its gate connected to a voltagegenerator, the NMOS transistor Q8 has its gate connected to the node N8and the PMOS transistor Q9 has its gate connected to the ground voltagesource Vss. The voltage generator is adapted to generate a voltage2Vcc/3.

FIG. 6 is a circuit diagram illustrating the construction of aconventional input buffer for a semiconductor memory device. As shown inthis drawing, the conventional input buffer comprises a PMOS transistorQ10 connected between nodes N10 and N11, a PMOS transistor Q11 connectedbetween the node N10 and a node N14, an NMOS transistor Q12 connectedbetween the node N11 and a node N12, an NMOS transistor Q13 connectedbetween the node N12 and a ground voltage source Vss, an NMOS transistorQ14 connected between the node N11 and a node N13, an NMOS transistorQ14 connected between the node N13 and the ground voltage source Vss, anNMOS transistor Q16 connected between the node N14 and a node N15, anNMOS transistor Q17 connected between the node N15 and the groundvoltage source Vss, an NMOS transistor Q18 connected between the nodeN14 and a node N16, and an NMOS transistor Q19 connected between thenode N16 and the ground voltage source Vss. The PMOS transistors Q10 andQ11 have their gates connected in common to the node N11. The NMOStransistor Q12 has its gate for inputting an internal reference voltageVref₋₋ int, the NMOS transistor Q13 has its gate connected to the LVTTL,the NMOS transistor Q14 has its gate for inputting a reference voltageVref, and the NMOS transistor Q15 has its gate connected to thehigh-speed I/O interface. The NMOS transistor Q16 has its gate forreceiving an input signal in, the NMOS transistor Q17 has its gateconnected to the high-speed I/O interface, the NMOS transistor Q18 hasits gate for receiving the input signal in, and the NMOS transistor Q19has its gate connected to the LVTTL.

The operations of the conventional automatic mode selection circuit andinput buffer with the above-mentioned constructions will hereinafter bedescribed with reference to FIGS. 5 and 6.

In FIG. 5, the PMOS transistors Q5 and Q6 and the NMOS transistors Q7and Q8 constitute a comparator 201. The comparator 201 compares thevoltage 2Vcc/3 at the gate of the NMOS transistor Q7 with the referencevoltage Vref at the gate of the NMOS transistor Q8 and supplies thecompared result to the node N6. Noticeably, because the high-speed I/Ointerface uses the reference voltage Vref from the external referencevoltage pad, it requires no additional means for generating thereference voltage Vref. The reference voltage Vref has a half voltagelevel Vcc/2, thereby making the high-speed I/O interface high in logic.The LVTTL receives no reference voltage. As a result, the PMOStransistor Q9 transfers the supply voltage Vcc from the supply voltagesource to the LVTTL, thereby making the LVTTL high in logic.

In FIG. 6, in the case where the LVTTL is selected by the automatic modeselection circuit, the internal reference voltage Vref₋₋ int is used bythe NMOS transistors Q12 and Q13. In the case where the high-speed I/Ointerface is selected by the automatic mode selection circuit, thereference voltage Vref is used by the NMOS transistors Q14 and Q15.

Noticeably, the output of the automatic mode selection circuit may beused in a data output buffer.

The above-mentioned conventional automatic mode selection circuit hasthe following disadvantages.

Firstly, the automatic mode selection circuit requires a voltagegenerator for generating the voltage 3Vcc/3.

Secondly, the automatic mode selection circuit requires means forswitching the LVTTL/high-speed I/O interface as shown in FIG. 6. Thisresults in the circuit becoming complicated and the speed being thusreduced.

Thirdly, in the case where the automatic mode selection circuit selectsthe high-speed I/O interface, the PMOS transistor Q9 transfers thesupply voltage Vcc from the supply voltage source to the node N8,resulting in the formation of a current path to the reference voltagepad 202.

SUMMARY OF THE INVENTION

Therefore, the present invention has been made in view of the aboveproblems, and it is an object of the present invention to provide anautomatic mode selection circuit for a semiconductor memory device whichis capable of automatically selecting two modes of LVTTL and high-speedI/O interface in the chip.

In accordance with an aspect of the present invention, there is providedan automatic mode selection circuit for automatically selecting lowvoltage transistor transistor logic and high-speed input/outputinterface modes in a semiconductor memory device, comprising externalreference voltage delivery means for delivering an external referencevoltage; internal reference voltage generation means for generating aninternal reference voltage; power-on detection means for detecting apower-on time point and then generating a pulse signal for apredetermined time period; switching means for switching the externalreference voltage from the external reference voltage delivery means anthe internal reference voltage from the internal reference voltagegeneration means in response to an output signal from the power-ondetection means; reference voltage detection means connected between theexternal reference voltage delivery means and the switching means fordetecting the external reference voltage from the external referencevoltage delivery means; comparison means for comparing an output voltagefrom the reference voltage detection means with the internal referencevoltage from the internal reference voltage generation means in responseto the output signal from the power-on detection means; and latch meansfor latching an output signal from the comparison means and supplyingthe latched signal to an output terminal.

In accordance with another aspect of the present invention, there isprovided an automatic mode selection circuit with an output terminal forautomatically selecting low voltage transistor transistor logic andhigh-speed input/output interface modes in a semiconductor memorydevice, comprising external reference voltage delivery means fordelivering an external reference voltage; internal reference voltagegeneration means for generating an internal reference voltage; power-ondetection means for detecting a power on time point and then generatinga pulse signal for a predetermined time period; first and secondswitching means for switching the external reference voltage from theexternal reference voltage delivery means and the internal referencevoltage from the internal reference voltage generation means in responseto first and second switching signals from the power-on detection meansand an output signal from the output terminal; reference voltagedetection means connected between the external reference voltagedelivery means and the switching means for detecting the externalreference voltage from the external reference voltage delivery means;comparison means for comparing an output voltage from the referencevoltage detection means with the internal reference voltage from theinternal reference voltage generation means when the first and secondswitching means are temporarily turned off; and latch means for latchingan output signal from the comparison means and supplying the latchedsignal to the output terminal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a table illustrating the comparison between voltage levels ofLVTTL and high-speed I/O interface;

FIG. 2 is a circuit diagram illustrating one example of the LVTTL;

FIG. 3 is a circuit diagram illustrating one example of the high-speedI/O interface;

FIG. 4 is a waveform diagram illustrating output signals from the LVTTLand high-speed I/O interface in FIGS. 2 and 3;

FIG. 5 is a circuit diagram illustrating the construction of aconventional automatic mode selection circuit for a semiconductor memorydevice;

FIG. 6 is a circuit diagram illustrating the construction of aconventional input buffer for a semiconductor memory device;

FIG. 7 is a block diagram illustrating the construction of an automaticmode selection circuit for a semiconductor memory device in accordancewith an embodiment of the present invention;

FIG. 8 is a detailed circuit diagram of a power-on detector in FIG. 7;

FIG. 9 is a detailed circuit diagram of a reference voltage detector anda switching circuit in FIG. 7;

FIG. 10 is a detailed circuit diagram of an alternative embodiment ofthe reference voltage detector in FIG. 7;

FIG. 11 is a detailed circuit diagram of a comparator and a latchcircuit in FIG. 7;

FIG. 12 is a detailed circuit diagram of an alternative embodiment ofthe comparator in FIG. 7;

FIG. 13 is a detailed circuit diagram of an input buffer in FIG. 7;

FIG. 14 is a waveform diagram illustrating the operation of theautomatic mode selection circuit for the semiconductor memory device inaccordance with the embodiment of the present invention;

FIG. 15 is a block diagram illustrating the construction of an automaticmode selection circuit for a semiconductor memory device in accordancewith an alternative embodiment of the present invention;

FIG. 16 is a detailed circuit diagram of a power-on detector in FIG. 15;and

FIG. 17 is a waveform diagram illustrating the operation of theautomatic mode selection circuit for the semiconductor memory device inaccordance with the alternative embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 7, there is shown a block diagram of an automatic modeselection circuit for a semiconductor memory device in accordance withan embodiment of the present invention. As shown in this drawing, theautomatic mode selection circuit comprises an external reference voltagepad 300 for delivering an external reference voltage Vref, an internalreference voltage generator 320 for generating an internal referencevoltage Vref₋₋ int, and a switching circuit 310 connected between theexternal reference voltage pad 300 and the internal reference voltagegenerator 320.

The automatic mode selection circuit further comprises a power-ondetector 340 connected to the switching circuit 310. The power-ondetector 340 is adapted to detect a power-on time point and thengenerate a pulse signal for a predetermined time period. The switchingcircuit 310 is operated in response to an output signal from thepower-on detector 340 to temporarily turn off the external referencevoltage pad 300 and the internal reference voltage generator 320.

The automatic mode selection circuit further comprises a referencevoltage detector 330 connected between the external reference voltagepad 300 and the switching circuit 310. The reference voltage detector330 is adapted to detect the external reference voltage Vref from theexternal reference voltage pad 300. If the reference voltage detector330 detects the external reference voltage Vref from the externalreference voltage pad 300, the present mode is a high-speed I/Ointerface mode. On the contrary, if the reference voltage detector 330detects no voltage from the external reference voltage pad 300, thepresent mode is an LVTTL mode.

The automatic mode selection circuit further comprises a comparator 350for comparing an output voltage Vd from the reference voltage detector330 with the internal reference voltage Vref₋₋ int from the internalreference voltage generator 320 in response to the output signal fromthe power-on detector 340, and a latch circuit 360 connected to anoutput terminal of the comparator 350. Upon the generation of an outputsignal from the latch circuit 360, the switching circuit 310 connectsthe external reference voltage pad 300 and the internal referencevoltage generator 320 to each other and then supplies a voltage at anode N41 to an input buffer. The latch circuit 360 may supply its outputsignal for discrimination between the LVTTL and high-speed I/O interfacemodes to a data output buffer.

For example, in a semiconductor memory device such as a synchronousdynamic random access memory, a mode register set operation must beperformed to prescribe states in the chip such as a burst length, adelay time of a signal CAS, etc. after power is turned on.

For example, in a semiconductor memory device such as a synchronousdynamic random access memory, a mode register set operation must beperformed to prescribe states in the chip such as a burst length, adelay time of a signal CAS, etc. after power is turned on.

Referring to FIG. 8, there is shown a detailed circuit diagram of thepower-on detector 340 in FIG. 7. As shown in this drawing, the power-ondetector 340 includes an inverter G2, a latch circuit 341 and a delaycircuit 342. The inverter G2 is connected between nodes N25 and N26. Thelatch circuit 341 includes two NAND gates G3 and G4 connected among thenode N26 and nodes N27 and N28. The node N25 is applied with a moderegister set signal mregst and the node N27 is applied with a power-upsignal pwrup. The delay circuit 342 includes five inverters G5-G9connected in series between the node N28 and a node N29, a NAND gate G10for NANDing signals at the nodes N28 and N29 and supplying the NANDedresult to a node N30, and an inverter G11 connected to the node N30. Apower-on detection signal pwron₋₋ det is supplied through the node N28.The inverter G11 provides its output signal to the switching circuit310.

Referring to FIG. 9, there is shown a detailed circuit diagram of thereference voltage detector 330 and switching circuit 310 in FIG. 7. Asshown in this drawing, the reference voltage detector 330 includes aPMOS transistor Q20 connected between a supply voltage source Vcc and anode N21. The PMOS transistor Q20 has its gate connected to a node N32.The switching circuit 310 includes a transfer transistor Q21 connectedbetween a node N31 and the node N32. The node 31 is applied with theoutput signal from the power-on detector 340. The transfer transistorQ21 is adapted to switch voltages at the nodes N21 and N41. The node N21is connected to the external reference voltage pad 300 and the node N41is connected to the internal reference voltage generator 320.

Referring to FIG. 10, there is shown a detailed circuit diagram of analternative embodiment of the reference voltage detector 330 in FIG. 7.As shown in this drawing, the reference voltage detector 330 includes anNMOS transistor Q23 connected between the node N21 and a node N51. TheNMOS transistor Q23 has its gate connected to the supply voltage sourceVcc. The node N21 is connected to the external reference voltage pad 300and the node N51 is connected to the comparator 350.

The reference voltage detector 330 further includes an NMOS transistorQ24 connected between the node N51 and a ground voltage source Vss. TheNMOS transistor Q24 has its gate connected to the node N31 which isapplied with the output signal from the power-on detector 340.

The reference voltage detector 330 further includes an NMOS transistorQ22 connected between the supply voltage source Vcc and the node N21.The NMOS transistor Q22 has its gate connected in common to theswitching circuit 310 and an inverter G12.

Referring to FIG. 11, there is shown a detailed circuit diagram of thecomparator 350 and latch circuit 360 in FIG. 7. As shown in thisdrawing, the comparator 350 includes PMOS transistors Q25 and Q26connected in parallel between nodes N58 and N59, an NMOS transistor Q29connected between the node N59 and a node N60, PMOS transistors Q27 andQ28 connected in parallel between the node N58 and a node N61, an NMOStransistor Q30 connected between the node N61 and the node N60, and anNMOS transistor Q31 connected between the node N60 and the groundvoltage source Vss. The PMOS transistor Q25 has its gate connected tothe node N51 and the PMOS transistor Q26 has its gate connected to thenode N59. The NMOS transistor Q29 has its gate for inputting a voltage2Vcc/3 from a voltage generator, the PMOS transistor Q27 has its gateconnected to the node N59 and the PMOS transistor Q28 has its gateconnected to the node N51. The NMOS transistor Q30 has its gateconnected to the external reference voltage pad 300 and the NMOStransistor Q31 has its gate connected to the node N51. The latch circuit360 includes two NAND gates G13 and G14 for latching a voltage at thenode N61 and outputting the latched voltage to a node N62 which isconnected to the LVTTL, and an inverter G15 connected between the nodeN62 and a node N71 which is connected to the high-speed I/O interface.

Referring to FIG. 12, there is shown a detailed circuit diagram of analternative embodiment of the comparator 350 in FIG. 7. The constructionof FIG. 12 is the same as that of FIG. 11, with the exception that theNMOS transistor Q29 inputs the internal reference voltage Vref₋₋ intfrom the internal reference voltage generator 320 at its gate and theNMOS transistor Q30 inputs the output voltage Vd from the referencevoltage detector 330 at its gate.

Referring to FIG. 13, there is shown a detailed circuit diagram of theinput buffer in FIG. 7. As shown in this drawing, the input buffercomprises a PMOS transistor Q32 connected between nodes N42 and N43, anNMOS transistor Q34 connected between the node N43 and a node N45, aPMOS transistor Q33 connected between the node N42 and a node N44, andan NMOS transistor Q35 connected between the nodes N44 and N45. The PMOStransistor Q32 has its gate connected to the node N43 and the PMOStransistor Q34 has its gate connected to the node N41. The PMOStransistor Q33 has its gate connected to the node N43 and the NMOStransistor Q35 has its gate for receiving an input signal in. The nodeN45 is connected to the ground voltage source Vss. With thisconstruction, the input buffer acts to compare a voltage at the node N41and the input signal in with each other and to output the comparedresult to the node N44.

The operation of the automatic mode selection circuit for thesemiconductor memory device with the above-mentioned construction inaccordance with the embodiment of the present invention will hereinafterbe described in detail with reference to FIGS. 8 to 14. FIG. 14 is awaveform diagram illustrating the operation of the automatic modeselection circuit for the semiconductor memory device in accordance withthe embodiment of the present invention.

First, in FIG. 8, when the mode register set signal mregst goes from lowto high in logic and the power-up signal pwrup is high in logic, thelatch circuit 341 supplies the power-on detection signal pwron₋₋ det ofhigh logic level to the node N28. The inverters G5-G9, NAND gate G10 andinverter G11 cooperate to input the power-on detection signal pwron₋₋det at the node N28 and output a high logic edge signal to the switchingcircuit 310. At this time, the edge signal has a pulse width delayed forthe predetermined time period.

In FIG. 9, in response to the high logic switching signal from thepower-on detector 340, the transfer transistor Q21 is turned off and thePMOS transistor Q20 is turned on. The transfer transistor Q21 and thePMOS transistor Q20 remain at their OFF and ON states for a propagationdelay time of the inverters G5-G9, NAND gate G10 and inverter G11 inFIG. 8 (see FIG. 14). As the PMOS transistor Q20 is turned on, itsupplies the output voltage Vd to the node N21.

In FIG. 11, the comparator 350 compares the output voltage Vd from thereference voltage detector 330 with the voltage 2Vcc/3 from the voltagegenerator and supplies the compared result to the latch circuit 360. Atthis time, the comparator 350 is controlled in response to the switchingsignal from the power-on detector 340.

Referring again to FIG. 9, when the switching signal from the power-ondetector 340 goes from high to low in logic, the transfer transistor Q21is turned on and the PMOS transistor Q20 is turned off. As a result, theexternal reference voltage pad 300 and the internal reference voltagegenerator 320 are connected to each other and the external referencevoltage from the external reference voltage pad 300 is supplied to theinput buffer through the node N41.

In FIG. 10, when the signal at the node N31 is high in logic, thetransfer transistor Q21 is turned off and the PMOS transistor Q22 isturned on. As a result, the NMOS transistor Q23 transfers the supplyvoltage Vcc to the comparator 350 through the node N21.

In FIG. 12, the comparator 350 compares the output voltage Vd from thereference voltage detector 330 with the internal reference voltageVref₋₋ int from the internal reference voltage generator 320 andsupplies the compared result to the latch circuit 360. At this time, thecomparator 350 is controlled in response to the switching signal fromthe power-on detector 340.

Referring to FIG. 15, there is shown a block diagram of an automaticmode selection circuit for a semiconductor memory device in accordancewith an alternative embodiment of the present invention. As shown inthis drawing, the automatic mode selection circuit comprises an externalreference voltage pad 400 for delivering an external reference voltageVref to a node N52, an internal reference voltage generator 410 forgenerating an internal reference voltage Vref₋₋ int and supplying thegenerated internal reference voltage Vref₋₋ int to a node N54, andtransfer transistors Q41 and Q42 connected in series between the nodesN52 and N54 for transferring a signal at the node N52 or at the node N54to an input buffer.

The automatic mode selection circuit further comprises a power-ondetector 450 for detecting a power-on time point and then supplying apulse signal with a predetermined period to nodes N59 and N60, a firstswitching circuit 420 connected among the node N59 and nodes N57 and N63for performing a switching operation in response to a first switchingsignal from the power-on detector 450, and a second switching circuit430 connected among a node N58 and the nodes N60 and N63 for performinga switching operation in response to a second switching signal from thepower-on detector 450.

The automatic mode selection circuit further comprises a referencevoltage detector 440 connected between the node N52 and a node N61 fordetecting the external reference voltage Vref from the externalreference voltage pad 400, a comparator 460 for comparing an outputvoltage from the reference voltage detector 440 with the internalreference voltage Vref₋₋ int from the internal reference voltagegenerator 410, and a latch circuit 470 for latching an output signalfrom the comparator 460 and supplying the latched signal to the nodeN63.

Referring to FIG. 16, there is shown a detailed circuit diagram of thepower-on detector 450 in FIG. 15. As shown in this drawing, the power-ondetector 450 includes an inverter G16, a latch circuit 480, and firstand second switching signal generators 490 and 500. The inverter G16 isconnected between nodes N80 and N81. The latch circuit 380 includes twoNAND gates G17 and G18 connected among the node N81 and nodes N82 andN83. The node N80 is applied with a mode register set signal mregst andthe node N82 is applied with a power-up signal pwrup. The firstswitching signal generator 490 includes three inverters G19-G21connected in series between the node N83 and a node N84, a NAND gate G22for NANDing signals at the nodes N83 and N84 and supplying the NANDedresult to a node N85, an inverter G23 connected between the node N85 anda node N86, a NAND gate G24 for NANDing a signal at the node N86 and asignal at a node N87 and supplying the NANDed result to a node N88, aninverter G27 connected between the node N87 and a node N89, and two NANDgates G25 and G26 connected among the nodes N88, N59 and N89. The NANDgates G25 and G26 constitute a latch circuit. The first switching signalis supplied through the node N59. The second switching signal generator500 includes an inverter G28 connected between the node N89 and a N90,and two NAND gates G29 and G30 connected among the nodes N90, N60 andN83. The second switching signal is supplied through the node N60.

The operation of the automatic mode selection circuit for thesemiconductor memory device with the above-mentioned construction inaccordance with the alternative embodiment of the present invention willhereinafter be described in detail with reference to FIGS. 15 to 17.FIG. 17 is a waveform diagram illustrating the operation of theautomatic mode selection circuit for the semiconductor memory device inaccordance with the alternative embodiment of the present invention.

Upon detecting a power-on time point, the power-on detector 450 outputsthe first and second switching signals to the first and second switchingcircuits 420 and 430, respectively. In response to the first switchingsignal from the power-on detector 450, the first switching circuit 420turns the transfer transistor Q41 off. The second switching circuit 430turns the transfer transistor Q42 on in response to the second switchingsignal from the power-on detector 450. In the case where the transfertransistor Q41 is turned on and the transfer transistor Q42 is turnedoff, the external reference voltage Vref from the external referencevoltage pad 400 is supplied as a reference voltage to the input bufferthrough a node N53. In this case, the present mode is the high-speed I/Ointerface mode. On the contrary, in the case where the transfertransistor Q41 is turned off and the transfer transistor Q42 is turnedon, the internal reference voltage Vref₋₋ int from the internalreference voltage generator 410 is supplied as the reference voltage tothe input buffer through the node N53. In this case, the present mode isthe LVTTL mode.

As mentioned above, in accordance with the present invention, theautomatic mode selection circuit detects the reference voltage statewhen power is initially turned on. The automatic mode selection circuitthen supplies the detected result to a component for discriminationbetween the LVTTL and high-speed I/O interface modes, such as a dataoutput buffer. When the detection of the reference voltage state hasbeen completed, the switching circuit 310 connects the externalreference voltage pad 300 and the internal reference voltage generator320 to each other so that they can be used in the input buffer.

The external reference voltage from the external reference voltage pad300 is transferred to the input buffer in the high-speed I/O interfacemode and the internal reference voltage Vref₋₋ int from the internalreference voltage generator 410 is transferred to the input buffer inthe LVTTL mode. Therefore, no additional means is required to switch theLVTTL and high-speed I/O interface modes.

The PMOS transistors Q20 and Q23 remain at their ON states only for aninterval that the transfer transistor Q21 remains at its OFF state.Therefore, even in the case where the high-speed I/O interface mode isselected, the PMOS transistors Q20 and Q22 form no current path to theexternal reference voltage pad 300 differently from the PMOS transistorQ9 in FIG. 5.

In FIG. 12, the comparator 350 inputs the internal reference voltageVref₋₋ int from the internal reference voltage generator 410. Therefore,there is no necessity for using the voltage generator for generating thevoltage 2Vcc/3.

In FIG. 10, assuming that the PMOS transistor Q22 has an impedance lowerthan that of the NMOS transistor Q23, and Q23:Q24=R:3R, where is aresistance, the output voltage Vd from the reference voltage detector330 can be obtained as follows:

    Vd÷3Vref/4=3/4×(Vcc/2)=3Vcc/8                    (1)

    Vd=3Vcc/4=6Vcc/8                                           (2)

    Vref.sub.-- int=Vcc/2=4Vcc/8

The above equation (1) corresponds to the high-speed I/O interface modeand the above equation (2) corresponds to the LVTTL mode. The LVTTL andhigh-speed I/O interface modes can be discriminated therebetween on thebasis of the above equations (1) and (2).

As apparent from the above description, according to the presentinvention, the automatic mode selection circuit for the semiconductormemory device can automatically select the two modes of LVTTL andhigh-speed I/O interface in the chip. Therefore, the present inventionhas the effect of reducing an occupied area on the chip and enhancingthe operation speed.

Although the preferred embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

I claim:
 1. An automatic mode selection circuit for automaticallyselecting low voltage transistor transistor logic and high-speedinput/output interface modes in a semiconductor memory device,comprising:external reference voltage delivery means for generating anexternal high-speed input/output reference voltage when a high-speedinput/output mode is operating; internal reference voltage generationmeans for generating an internal transistor transistor logic referencevoltage; power-on detection means for detecting a power-on time pointand then generating a pulse signal for a predetermined time period;switching means for switching the external reference voltage from saidexternal reference voltage delivery means and the internal referencevoltage from said internal reference voltage generation means inresponse to an output signal from said power-on detection means;reference means detection means connected between said externalreference voltage delivery means and said switching means for detectingwhether the external reference voltage from said external referencevoltage delivery means is present, said reference voltage detectionmeans being adapted to output a difference voltage level in each case bydetecting the external reference voltage from said external voltagedelivery means in the high-speed input/output interface mode or a powersupply voltage in the low voltage transistor transistor logic mode;comparison means for comparing an output voltage from said referencevoltage detection means with the internal reference voltage from saidinternal reference voltage generation means in response to the outputsignal from said power-on detection means, said comparison means beingadapted to compare the output voltage level from said reference voltagedetection means with a 2/3 voltage level of the power supply voltage;and latch means for latching an output signal from said comparison meansand supplying the latched signal to an output terminal.
 2. An automaticmode selection circuit as set forth in claim 1, wherein said power-ondetector means includes:inversion means for inverting a mode registerset signal; latch means for generating a power-on detection signal inresponse to an output signal from said inversion means and a power-onsignal; and delay means for delaying the power-on detection signal fromsaid latch means and supplying the delayed power-on detection signal asa switching signal to said switching means.
 3. An automatic modeselection circuit as set forth in claim 1, wherein said switching meansincludes a transfer transistor connected between said external referencevoltage delivery means and said internal reference voltage generationmeans, for switching the external reference voltage from said externalreference voltage delivery means and the internal reference voltage fromsaid internal reference voltage generation means in response to theoutput signal from said power-on detection means.
 4. An automatic modeselection circuit as set forth in claim 1, wherein said referencevoltage detection means includes a PMOS transistor connected between asupply voltage source and a node between said external reference voltagedelivery means and said internal reference voltage generation means,said PMOS transistor being controlled in response to an output signalfrom said switching means and the output signal from said power-ondetection means.
 5. An automatic mode selection circuit as set forth inclaim 1, wherein said reference voltage detection means includes:a PMOStransistor connected between a supply voltage source and a node betweensaid external reference voltage delivery means and said internalreference voltage generation means, said PMOS transistor beingcontrolled in response to an output signal from said switching means andthe output signal from said power-on detection means; a first NMOStransistor connected between said node and said comparison means, saidfirst NMOS transistor having its gate connected to said supply voltagesource; and a second NMOS transistor connected between said comparisonmeans and a ground voltage source, said second NMOS transistor havingits gate for inputting the output signal from said power-on detectionmeans.
 6. An automatic mode selection circuit as set forth in claim 1,further comprising an input buffer connected between said switchingmeans and said internal reference voltage generation means, said inputbuffer comparing a signal transferred by said switching means with aninput signal.
 7. An automatic mode selection circuit with an outputterminal for automatically selection low voltage transistor transistorlogic and high-speed input/output interface modes in a semiconductormemory device, comprising:external reference voltage delivery means fordelivering an external high-speed input/output reference voltage;internal reference voltage generation means for generating an internaltransistor transistor logic reference voltage; power-on detection meansfor detecting a power-on time point and then generating a pulse signalfor a predetermined time period; first and second switching means forswitching the external reference voltage from said external referencevoltage delivery means and the internal reference voltage from saidinternal reference voltage generation means in response to first andsecond switching signals from said power-on detection means and anoutput signal from said output terminal; reference voltage detectionmeans connected between said external reference voltage delivery meansand said switching means for detecting the external reference voltagefrom said external reference voltage delivery means, said referencevoltage detection means being adapted to output a difference voltagelevel in each case by detecting the external reference voltage from saidexternal voltage delivery means in the high-speed input/output interfacemode or a power supply voltage in the low voltage transistor transistorlogic mode; comparison means for comparison an output voltage from saidreference voltage detection means with the internal reference voltagefrom said internal reference voltage generation means when said firstand second switching means are temporarily turned off, said comparisonmeans being adapted to compare the output voltage level from saidreference voltage detection means with a 2/3 voltage level of the powersupply voltage; and latch means for latching an output signal from saidcomparison means and supplying the latched signal to said outputterminal.
 8. An automatic mode selection circuit as set forth in claim7, wherein said power-on detection means includes:inversion means forinverting a mode register set signal; latch means for generating apower-on detection signal in response to an output signal from saidinversion means and a power-up signal; and first and second switchingsignal generation means for generating the first and second switchingsignals in response to the power-on detection signal from said latchmeans and a low voltage transistor transistor logic signal and supplyingthe generated first and second switching signals to said first andsecond switching means, respectively.
 9. An automatic mode selectioncircuit for automatically selecting low voltage transistor transistorlogic and high-speed input/output interface modes in a semiconductormemory device, comprising:external reference voltage delivery means fordelivering an external high-speed input/output reference voltage when ahigh-speed input/output mode is operating; internal reference voltagegeneration means for generating an internal transistor transistor logicreference voltage; power-on detection means for detecting power-on timepoint and then generating a pulse signal for a predetermined timeperiod; switching means for switching the external reference voltagefrom said external reference voltage delivery means and the internalreference voltage from said internal reference voltage generation meansin response to an output signal from said power-on detection means;reference voltage detection means connected between said externalvoltage delivery means and said switching means for detecting theexternal reference voltage from said external reference voltage deliverymeans; comparison means for comparing an output voltage from saidreference voltage detection means with the internal reference voltagefrom said internal reference voltage generation means in response to theoutput signal from said power-on detection means; and latch means forlatching an output signal from said comparison means and supplying to anoutput terminal a power supply voltage in the low voltage transistortransistor mode and an external reference voltage in the high-speedinput/output mode; wherein said reference voltage detection means isadapted to output a different voltage level in each case by detectingthe external reference voltage from said external reference voltagedelivery means in the high-speed input/output interface mode or a powersupply voltage in the low voltage transistor transistor logic mode, saidcomparison means is adapted to compare the output voltage level fromsaid reference voltage detection means with a 2/3 voltage level of thepower supply voltage, said switching means includes a transfertransistor connected between said external reference voltage deliverymeans and said internal reference voltage generation means, forswitching the external reference voltage from said external voltagedelivery means and the internal reference voltage from said from saidinternal reference voltage generation means in response to the outputsignal from said power-on detection means, and said reference voltagedetection means includes a PMOS transistor connected between a supplyvoltage source and a node between said external reference voltagedelivery means and said internal voltage generation means, said PMOStransistor being controlled in response to an output signal from saidswitching means and the output signal from said power-on detectionmeans.